1. Field
Aspects of the present disclosure relate generally to phase-locked loops (PLLs), and more particularly, to reducing the noise and power consumption in a switched-capacitor loop filter for a PLL.
2. Background
A phase-locked loop (PLL) is a closed-loop frequency-control system that adjusts the frequency of an output signal to minimize the phase or frequency difference between a reference signal and a feedback signal. The feedback signal may be generated by passing the output signal through a frequency divider. PLLs are widely used to provide signals having a desired frequency and/or phase in wireless communication systems, micro-processing systems, and high-speed data conversion systems.
A PLL typically comprises a loop filter to stabilize the PLL and/or reduce jitter. The loop filter may be implemented using a resistor-capacitor (RC) loop filter. However, the capacitor in an RC loop filter typically consumes a large chip area, and therefore may not be suitable for circuit integration. Alternatively, the loop filter may be implemented using an active switched-capacitor loop filter. An advantage of using an active switched-capacitor loop filer is that it requires less space than an RC loop filter, making the PLL more area efficient. However, an active switch-capacitor loop filter may experience noise and high power consumption caused by active elements in the active switched-capacitor loop filter.